The HT5700 is a single-chip HART FSK half-duplex modem that meets the HART physical layer specification. It integrates the filtering, signal detection, modulation, demodulation, and signal generation a HART device needs, so the design around it takes very few external components. The chip also carries a 0.5%-precision internal oscillator, which removes the external crystal in space- or cost-constrained designs.

It is supplied in a 4 mm × 4 mm 24-lead QFN package and is controlled over a standard UART interface (RTS, CD, TXD, RXD).

Features

• HART-compliant, fully integrated FSK modem
• 115 µA maximum supply current in receive mode
• Suitable for intrinsically safe applications
• Integrated receive band-pass filter — minimal external components
• Three clocking options: ultralow-power crystal oscillator (60 µA maximum), external CMOS clock, or precision internal oscillator
• Buffered HART output with extra drive capability
• 8 kV HBM ESD rating
• 2.7 V to 5.5 V supply; 1.71 V to 5.5 V digital interface
• −40 °C to +125 °C operation
• UART interface

Applications

• Field transmitters
• HART multiplexers
• PLC and DCS analog I/O modules
• HART network connectivity

How It Works

HART carries digital data across the analog 4–20 mA wiring by modulating a 1 mA peak-to-peak FSK signal on top of the loop current. The HT5700 generates and recovers that signal as a half-duplex modem: a 1.2 kHz tone is a mark (digital 1) and a 2.2 kHz tone is a space (digital 0).

On transmit, the modulator turns the UART bit stream at TXD into 1200 Hz / 2200 Hz tones, which are buffered and driven out on HART_OUT. A DDS engine generates the sine waves in digital form, so the phase stays continuous across a frequency change and there is no output discontinuity. The modulator is enabled by bringing RTS low.

On receive, the demodulator takes the FSK signal at HART_IN, runs it through the ADC and digital filtering, and restores the bit stream at RXD. A high on the CD pin indicates a valid carrier is present. RTS high enables the demodulator and disables the modulator.

Filter Configuration

The HT5700 supports two receive-filter options, selected at the FILTER_SEL pin:

• Internal filter — the HART signal is applied to HART_IN through a 2.2 nF series capacitor. This option saves cost and board space by removing external filter components. It achieves the 8 kV HBM ESD rating but needs extra external EMC and surge protection in harsh industrial environments.
• External filter — the HART signal is applied to ADC_IP through an external band-pass filter. The recommended external filter includes a 150 kΩ resistor that limits current to a level suitable for intrinsic safety, and gives higher transient-voltage protection at the input.

Clock Configuration

Three clocking schemes are available, configured through the XTAL_EN, CLK_CFG0, and CLK_CFG1 pins:

• External crystal — a 3.6864 MHz crystal (e.g. ABLS-3.6864MHZ-L4Q-T) across XTAL1 and XTAL2; the crystal datasheet recommends two 18 pF load capacitors.
• External CMOS clock — drive XTAL1 from an external clock source and leave XTAL2 open.
• Internal RC oscillator — the 0.5%-precision RC oscillator runs at 1.2288 MHz and consumes typically 87 µA; tie XTAL1 to ground and leave XTAL2 open.

A buffered clock can be provided at the CLKOUT pin. With the crystal oscillator, CLKOUT can be 3.6864 MHz, 1.8432 MHz, or 1.2288 MHz; with the internal RC oscillator it is available as 1.2288 MHz. No CLKOUT is available when a CMOS clock is used.

Power-Down and Full-Duplex Modes

Holding RESET low places the device in power-down mode, where the receive, transmit, and oscillator circuits are switched off and the device draws typically 30 µA. When the internal reference is used, REF_EN can be tied to RESET so the reference powers down as well.

Setting the DUPLEX pin high enables full-duplex operation, in which the modulator and demodulator run at the same time. This supports a self-test of the HART device and the complete signal path between the device and the host, verifying that the local communications loop is functional — useful in production self-test and advantageous to an application’s SIL rating.

Key Specifications

Conditions: VCC = 2.7 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, −40 °C to +125 °C unless noted; typical at 25 °C.

Application Notes

For loop-powered designs, a series resistance on the VCC supply reduces the effect of current-draw variation on the loop; 470 Ω has proven effective in typical applications. Decouple VCC and IOVCC with 10 µF in parallel with 0.1 µF to ground, and decouple REG_CAP and REF each with a 1 µF ceramic capacitor. For transient protection in harsh environments, a TVS at the loop connection point and a series resistor at the FSK output are used; the 150 kΩ resistor in the external filter inherently protects the FSK input.

For the full pin descriptions, timing characteristics, and typical connection diagrams, see the HT5700 user manual, or contact Microcyber at info@microcyber.cn.